DUNE FIRMWARE FILE [hdbase3] format2 110127_2105_beta 87163392 1469123996 61388846 89263943 3215300 36589602 80551992 39607235 74004126 15325843 70133650 80164006
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r.3g
x.boot X z.stage1_ga x.pll.1.pll 0 x.mux z.verbose x.ddr.0.density x.ddr.1.density x.ddr.grade x.ddr.fmin_mhz } x.ddr.fmax_mhz M x.ddr.method XX x.ddr.verbose x.poison a.avclk_mux @ a.hostclk_mux 1 a.cd0_freq a.cd1_freq a.cd2_freq ظ a.cd3_freq a.cd5_freq a.cd6_freq a.cd7_freq a.cd8_freq a.cd9_freq a.cd10_freq a.cd11_freq a.irq_rise_edge_lo ( a.irq_rise_edge_hi a.irq_fall_edge_lo a.irq_fall_edge_hi a.gpio_irq_map
a.gpio_dir @ a.gpio_data @H a.pb_def_timing a.pb_cs_config 3 a.pb_cs_config1 a.pb_cs_ctrl a.pb_timing0 a.pb_use_timing0 a.uart0_gpio_mode n a.uart0_gpio_dir a.uart0_gpio_data a.uart0_baudrate a.uart1_baudrate a.board_id 957-E1 bxmb.comment --- review xmasboot/configs/957-E1.config for details [xmbb7-ezboot98-nand_st2] ---
a.enable_devices a.eth_mac 00:16:e8. a.eth1_mac 00:16:e8:00/25 a.sata_channel_cfg W z.boot0 H z.boot1 L z.boot2 z.imatromfs_offset L z.imatromfs_size ( z.imatromfs_mm z.xmatromfs_offset t z.xmatromfs_size z.xmatromfs_mm z.default_boot !z.interactive_boot_idx_sel z.bootdev_order y.testvar yamonfoo by.b0 nflash read 0x080000 0xa4a00000 0x040000 0; dump romfs 0xa4a00000; load zbf 0xa4a00080; go by.b1 nflash read 0x0c0000 0xa7000000 0x740000 0; dump romfs 0xa7000000; load zbf 0xa7000090; go by.b2 nflash read 0x000000 0xa4a00000 0x080000 0; dump romfs 0xa4a00000; load zbf 0xa4a00080; go cy.fb0 nflash read 0x080000 0x84a00000 0x040000 0; dump romfs 0x84a00000; load zbf 0x84a00080; go cy.fb1 nflash read 0x0c0000 0x87000000 0x740000 0; dump romfs 0x87000000; load zbf 0x87000090; go cy.fb2 nflash read 0x480000 0x84a00000 0x080000 0; dump romfs 0x84a00000; load zbf 0x84a00080; go y.spug load uu 0xa4a00000; cksum 0xa4a00000 0x20000; nflash erase -p 0 0x20000 0; nflash write -p 0 0xa4a00000 0x20000 0; nflash read -p 0 0xa4a00001 0x20000 0; cksum 0xa4a00001 0x20000 0y.lf nflash format 0; gw32 0x6f014 0x80000000 y.xenv_addr "0xbb79bcb0" y.commit nflash read -p 0 0xa4a00000 0x20000 0; copy $xenv_addr 0xa4a00000 0x4000; nflash erase -p 0 0x20000 0; nflash write -p 0 0xa4a00000 0x20000 0 y.ub go 0xa00e5284 l.cs0_size l.cs0_parts l.cs0_part1_offset l.cs0_part1_size l.cs0_part2_offset l.cs0_part2_size @ l.cs0_part3_offset H l.cs0_part3_size l.cs0_part4_offset L l.cs0_part4_size l.cs0_part5_offset l.cs0_part5_size l.cs0_part6_offset L l.cs0_part6_size ( l.cs0_part7_offset t l.cs0_part7_size l.cs0_part8_offset x l.cs0_part10_offset x l.cs0_part10_size l.cs0_part11_offset x l.cs0_part11_size l.cs0_part12_offset x l.cs0_part12_size l.cs0_part13_offset x l.cs0_part13_size l.cs0_part14_offset x l.cs0_part14_size l.cs0_part15_offset l.cs0_part15_size x l.cs1_size a.linux_cmd "mem=141m" z.log2_xpu0_size z.dsp0_size P z.zdata0_size @ z.uzdata0_size @ z.log2_xpu1_size z.dsp1_size @ z.zdata1_size @ z.uzdata1_size @ z.ruamm0_offset z.ruamm1_offset @ z.stage2_ga z.xos_public_mm z.log2_xos_public_size z.channel_index_mm z.ih_api_mm z.ios_mm z.ios_size @ z.splashscreen_enabled i.sp.scaler i.sp.digital_enable i.sp.component_enable i.sp.analog_enable i.sp.digital_standard # i.sp.component_standard e i.sp.analog_standard { i.sp.picture splash.sdd i.sp.hdmi_chip i.sp.animation_enable a.ps.mt3_hs 5+eE! 5+eE! }}||zz a.ps.pll2 ; a.ps.pll0 a.standby.mt3_hs /` a.standby.pll2 a.standby.pll0 a.standby.gpio_dir a.standby.gpio_data bdp.autostart bdp.fip.model fip0910 bdp.n.dns1 "0.0.0.0" bdp.n.dns2 "0.0.0.0" bdp.n.gateway "0.0.0.0" bdp.n.ipaddr "0.0.0.0" bdp.n.mask "0.0.0.0" bdp.n.status "static" dune.product_id "hdbase3" l.cs0_part8_size l.cs0_part9_offset | l.cs0_part9_size yww; }'yOQļl;. v[Q翏 2F&LwڹMa|z$stŘV&?{}h"G`7